<html><body><samp><pre>
<!@TC:1497825396>
#Build: Synplify Pro L-2016.09L+ice40, Build 077R, Dec  2 2016
#install: C:\lscc\iCEcube2.2017.01\synpbase
#OS: Windows 8 6.2
#Hostname: LAPOT

# Mon Jun 19 01:36:36 2017

#Implementation: HFOSC_TEST_Implmnt

<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1497825397> | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

<a name=compilerReport2></a>Synopsys Verilog Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1497825397> | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\generic\sb_ice40.v" (library work)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\top.v" (library work)
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module top
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\iCEcube2.2017.01\synpbase\lib\generic\sb_ice40.v:4020:7:4020:15:@N:CG364:@XP_MSG">sb_ice40.v(4020)</a><!@TM:1497825397> | Synthesizing module SB_HFOSC in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\top.v:1:7:1:10:@N:CG364:@XP_MSG">top.v(1)</a><!@TM:1497825397> | Synthesizing module top in library work.


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Jun 19 01:36:37 2017

###########################################################]
<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1497825397> | Running in 64-bit mode 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1497825397> | Selected library: work cell: top view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1497825397> | Selected library: work cell: top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Jun 19 01:36:37 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Jun 19 01:36:37 2017

###########################################################]
<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1497825399> | Running in 64-bit mode 
File D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\HFOSC_TEST_Implmnt\synwork\HFOSC_TEST_comp.srs changed - recompiling
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1497825399> | Selected library: work cell: top view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1497825399> | Selected library: work cell: top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Jun 19 01:36:39 2017

###########################################################]
Pre-mapping Report

# Mon Jun 19 01:36:39 2017

<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1612R, Built Dec  5 2016 10:31:39</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1497825401> | No constraint file specified. 
@L: D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\HFOSC_TEST_Implmnt\HFOSC_TEST_scck.rpt 
Printing clock  summary report in "D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\HFOSC_TEST_Implmnt\HFOSC_TEST_scck.rpt" file 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1497825401> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1497825401> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=18  set on top level netlist top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)



<a name=mapperReport6></a>Clock Summary</a>
*****************

Start                            Requested     Requested     Clock        Clock                     Clock
Clock                            Frequency     Period        Type         Group                     Load 
---------------------------------------------------------------------------------------------------------
top|o_clk_out_inferred_clock     6.0 MHz       166.640       inferred     Autoconstr_clkgroup_0     22   
=========================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="d:\drive\projects\lattice fpga\projects\hfosc_test\top.v:11:1:11:7:@W:MT529:@XP_MSG">top.v(11)</a><!@TM:1497825401> | Found inferred clock top|o_clk_out_inferred_clock which controls 22 sequential elements including counter[20:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

Finished Pre Mapping Phase.
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1497825401> | Writing default property annotation file D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\HFOSC_TEST_Implmnt\HFOSC_TEST.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 47MB peak: 133MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Mon Jun 19 01:36:41 2017

###########################################################]
Map & Optimize Report

# Mon Jun 19 01:36:41 2017

<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1612R, Built Dec  5 2016 10:31:39</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1497825407> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1497825407> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1497825407> | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 130MB peak: 133MB)

@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\drive\projects\lattice fpga\projects\hfosc_test\top.v:11:1:11:7:@N:MO231:@XP_MSG">top.v(11)</a><!@TM:1497825407> | Found counter in view:work.top(verilog) instance counter[20:0] 

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		   160.77ns		  28 /        22

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)



@S |Clock Optimization Summary


<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 22 clock pin(s) of sequential element(s)
0 instances converted, 22 sequential instances remain driven by gated/generated clocks

================================================================================================= Gated/Generated Clocks =================================================================================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance     Explanation                                                                                                                   
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|S:osc@|E:counter[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       osc                 SB_HFOSC               22         counter[0]          Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
==========================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 106MB peak: 133MB)

Writing Analyst data base D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\HFOSC_TEST_Implmnt\synwork\HFOSC_TEST_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 130MB peak: 133MB)

Writing EDIF Netlist and constraint files
@N:<a href="@N:BW103:@XP_HELP">BW103</a> : <!@TM:1497825407> | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:<a href="@N:BW107:@XP_HELP">BW107</a> : <!@TM:1497825407> | Synopsys Constraint File capacitance units using default value of 1pF  
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1497825407> | Writing EDF file: D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\HFOSC_TEST_Implmnt\HFOSC_TEST.edf 
L-2016.09L+ice40

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 131MB peak: 133MB)


Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 132MB peak: 133MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1497825407> | Found inferred clock top|o_clk_out_inferred_clock with period 166.64ns. Please declare a user-defined clock on object "n:o_clk_out"</font> 


<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Mon Jun 19 01:36:47 2017
#


Top view:               top
Requested Frequency:    6.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1497825407> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1497825407> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary10></a>Performance Summary</a>
*******************


Worst slack in design: 156.320

                                 Requested     Estimated     Requested     Estimated                 Clock        Clock                
Starting Clock                   Frequency     Frequency     Period        Period        Slack       Type         Group                
---------------------------------------------------------------------------------------------------------------------------------------
top|o_clk_out_inferred_clock     6.0 MHz       96.9 MHz      166.640       10.320        156.320     inferred     Autoconstr_clkgroup_0
=======================================================================================================================================





<a name=clockRelationships11></a>Clock Relationships</a>
*******************

Clocks                                                      |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------
Starting                      Ending                        |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------
top|o_clk_out_inferred_clock  top|o_clk_out_inferred_clock  |  166.640     156.320  |  No paths    -      |  No paths    -      |  No paths    -    
====================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo12></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport13></a>Detailed Report for Clock: top|o_clk_out_inferred_clock</a>
====================================



<a name=startingSlack14></a>Starting Points with Worst Slack</a>
********************************

                Starting                                                            Arrival            
Instance        Reference                        Type       Pin     Net             Time        Slack  
                Clock                                                                                  
-------------------------------------------------------------------------------------------------------
counter[0]      top|o_clk_out_inferred_clock     SB_DFF     Q       counter[0]      0.796       156.320
counter[19]     top|o_clk_out_inferred_clock     SB_DFF     Q       counter[19]     0.796       156.393
counter[1]      top|o_clk_out_inferred_clock     SB_DFF     Q       counter[1]      0.796       156.413
counter[2]      top|o_clk_out_inferred_clock     SB_DFF     Q       counter[2]      0.796       156.486
counter[3]      top|o_clk_out_inferred_clock     SB_DFF     Q       counter[3]      0.796       156.517
counter[4]      top|o_clk_out_inferred_clock     SB_DFF     Q       counter[4]      0.796       156.610
counter[15]     top|o_clk_out_inferred_clock     SB_DFF     Q       counter[15]     0.796       158.156
counter[16]     top|o_clk_out_inferred_clock     SB_DFF     Q       counter[16]     0.796       158.229
counter[17]     top|o_clk_out_inferred_clock     SB_DFF     Q       counter[17]     0.796       158.249
counter[20]     top|o_clk_out_inferred_clock     SB_DFF     Q       counter[20]     0.796       158.260
=======================================================================================================


<a name=endingSlack15></a>Ending Points with Worst Slack</a>
******************************

                Starting                                                              Required            
Instance        Reference                        Type       Pin     Net               Time         Slack  
                Clock                                                                                     
----------------------------------------------------------------------------------------------------------
o_led           top|o_clk_out_inferred_clock     SB_DFF     D       o_led_0           166.485      156.320
counter[20]     top|o_clk_out_inferred_clock     SB_DFF     D       counter_s[20]     166.485      158.317
counter[19]     top|o_clk_out_inferred_clock     SB_DFF     D       counter_s[19]     166.485      158.517
counter[18]     top|o_clk_out_inferred_clock     SB_DFF     D       counter_s[18]     166.485      158.717
counter[17]     top|o_clk_out_inferred_clock     SB_DFF     D       counter_s[17]     166.485      158.917
counter[16]     top|o_clk_out_inferred_clock     SB_DFF     D       counter_s[16]     166.485      159.117
counter[15]     top|o_clk_out_inferred_clock     SB_DFF     D       counter_s[15]     166.485      159.317
counter[14]     top|o_clk_out_inferred_clock     SB_DFF     D       counter_s[14]     166.485      159.517
counter[13]     top|o_clk_out_inferred_clock     SB_DFF     D       counter_s[13]     166.485      159.717
counter[12]     top|o_clk_out_inferred_clock     SB_DFF     D       counter_s[12]     166.485      159.917
==========================================================================================================



<a name=worstPaths16></a>Worst Path Information</a>
<a href="D:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\HFOSC_TEST_Implmnt\HFOSC_TEST.srr:srsfD:\Drive\Projects\Lattice FPGA\Projects\HFOSC_TEST\HFOSC_TEST_Implmnt\HFOSC_TEST.srs:fp:21233:22493:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      166.640
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         166.485

    - Propagation time:                      10.165
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     156.320

    Number of logic level(s):                4
    Starting point:                          counter[0] / Q
    Ending point:                            o_led / D
    The start point is clocked by            top|o_clk_out_inferred_clock [rising] on pin C
    The end   point is clocked by            top|o_clk_out_inferred_clock [rising] on pin C

Instance / Net                   Pin      Pin               Arrival     No. of    
Name                 Type        Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
counter[0]           SB_DFF      Q        Out     0.796     0.796       -         
counter[0]           Net         -        -       1.599     -           3         
o_led_RNO_5          SB_LUT4     I0       In      -         2.395       -         
o_led_RNO_5          SB_LUT4     O        Out     0.661     3.056       -         
proc_\.o_led3_2      Net         -        -       1.371     -           1         
o_led_RNO_4          SB_LUT4     I2       In      -         4.427       -         
o_led_RNO_4          SB_LUT4     O        Out     0.558     4.986       -         
proc_\.o_led3_16     Net         -        -       1.371     -           1         
o_led_RNO_2          SB_LUT4     I3       In      -         6.356       -         
o_led_RNO_2          SB_LUT4     O        Out     0.465     6.822       -         
proc_\.o_led3_18     Net         -        -       1.371     -           1         
o_led_RNO            SB_LUT4     I3       In      -         8.193       -         
o_led_RNO            SB_LUT4     O        Out     0.465     8.658       -         
o_led_0              Net         -        -       1.507     -           1         
o_led                SB_DFF      D        In      -         10.165      -         
==================================================================================
Total path delay (propagation time + setup) of 10.320 is 3.101(30.0%) logic and 7.219(70.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 132MB peak: 133MB)


Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 132MB peak: 133MB)

---------------------------------------
<a name=resourceUsage17></a>Resource Usage Report for top </a>

Mapping to part: ice5lp2ksg48
Cell usage:
SB_CARRY        20 uses
SB_DFF          22 uses
SB_HFOSC        1 use
SB_LUT4         29 uses

I/O ports: 1
I/O primitives: 1
SB_IO          1 use

I/O Register bits:                  0
Register bits not including I/Os:   22 (1%)
Total load per clock:
   top|o_clk_out_inferred_clock: 22

@S |Mapping Summary:
Total  LUTs: 29 (1%)

Distribution of All Consumed LUTs = LUT4 
Distribution of All Consumed Luts 29 = 29 

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 26MB peak: 133MB)

Process took 0h:00m:05s realtime, 0h:00m:04s cputime
# Mon Jun 19 01:36:47 2017

###########################################################]

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